AI 芯片工作原理：从逻辑门到矩阵乘法

How AI Chips Work: From Logic Gates to Matrix Multiplication

赖纳·波普 Reiner Pope · Dwarkesh 播客 · 2026-05-22 · 约 80 分钟 · 原视频 ↗

打开互动全文版（中英对照 + 朗读 + 问答）→

本期速览 · Overview

AI 芯片公司 Maddock CEO Rainer Pope 解释 AI 芯片的基本构建模块，从逻辑门到乘加运算。

Rainer Pope, CEO of AI chip company Maddock, explains the fundamental building blocks of AI chips, from logic gates to multiply-accumulate operations.

要点 · TL;DR

• AI 芯片依赖乘累加运算，通过脉动阵列优化以减少数据搬运。
  AI chips rely on multiply-accumulate operations, optimized by systolic arrays to reduce data movement.
• 低精度如 FP4 因面积二次缩放带来超线性效率提升。
  Low precision like FP4 offers super-linear efficiency gains due to quadratic area scaling.
• FPGA 用查找表模拟门电路，面积成本约 10 倍但可重编程。
  FPGAs use lookup tables to emulate gates, costing ~10x area but enabling reprogrammability.

核心观点 · Key points

• 乘加运算是AI芯片的基本单元，由矩阵乘法驱动。
  Multiply-accumulate is the fundamental primitive for AI chips, driven by matrix multiplication.
• 脉动阵列通过本地存储权重并重复使用，减少数据搬运开销。
  Systolic arrays reduce data movement overhead by storing weights locally and reusing them.
• 时钟周期同步对于芯片的大规模并行性至关重要。
  Clock cycle synchronization is essential for massive parallelism in chips.
• FPGA使用查找表和多路选择器模拟门电路，面积成本约为ASIC的10倍。
  FPGAs use lookup tables and muxes to emulate gates, costing ~10x area vs ASICs.
• 暂存器存储器提供确定性延迟，不同于CPU中的缓存。
  Scratchpad memory gives deterministic latency, unlike caches in CPUs.

反共识 · Contrarian takes

• 位宽的二次缩放使低精度比预期高效得多。
  Quadratic scaling with bit width makes low precision far more efficient than expected.
• 数据搬运成本在芯片内部也占主导，而不仅限于芯片之间。
  Data movement costs dominate compute costs even inside a chip, not just between chips.
• 由于面积二次缩放和指数开销，FP4吞吐量可达FP8的3倍而非2倍。
  FP4 throughput can be 3x FP8, not 2x, due to quadratic area scaling and exponent overhead.
• CPU可以实现确定性延迟，但因市场偏好而被避免。
  Deterministic latency in CPUs is possible but avoided due to market preferences.
• GPU本质上是许多小型TPU拼接而成，并非根本不同。
  GPUs are essentially many tiny TPUs tiled together, not fundamentally different.

本期章节 · Chapters（共 25）

• 引言与芯片基础 Introduction and chip basics
• 手动计算与逻辑门 Manual calculation and logic gates
• 全加器与进位传播 Full Adder and Carry Propagation
• Dadda乘法器与电路规模 Dadda Multiplier and Circuit Size
• 映射到物理逻辑门 Mapping to Physical Logic Gates
• FP4与FP8电路的可互换性 Fungibility of FP4 and FP8 Circuits
• 二次缩放与数据移动成本 Quadratic scaling and data movement costs
• Crusoe云性能 Crusoe cloud performance
• 多路复用器电路简介 Introduction to Multiplexer Circuit
• 脉动阵列的动机 Motivation for Systolic Arrays
• 优化脉动阵列中的矩阵乘法 Optimizing matrix multiplication in systolic arrays
• 时钟周期基础 Clock cycle basics
• 流水线寄存器插入与时钟速度权衡 Pipeline Register Insertion and Clock Speed Trade-offs
• 交易作为AGI完备问题与Jane Street招聘 Trading as AGI-complete and Jane Street's hiring
• FPGA在高频交易中的应用原因 Why FPGAs are used in high-frequency trading
• FPGA如何模拟ASIC模型 How an FPGA emulates the ASIC model
• “现场编程”的含义 What 'programmed in the field' means
• 查找表内部 Inside the lookup table (LUT)
• FPGA与ASIC成本对比 FPGA vs ASIC cost
• FPGA与CPU的确定性延迟 Deterministic latency in FPGAs vs CPUs
• 暂存器与缓存 Scratchpad vs Cache
• 冯·诺依曼架构与并行性 Von Neumann Architecture and Parallelism
• 大脑与硬件对比 Brain vs Hardware
• 时钟速度与能效 Clock speed and energy efficiency
• GPU与TPU的高层区别 High-level difference between GPU and TPU

阅读全文双语转录 →